Introduction To Makefiles

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This page describes how to use the make utility to automatically build, clean, and package your projects.

Contents

[edit] What is Make?

Make is a small utility that will follow rules to compile and link programs from source. It is available on most Linux and Unix distributions (including Mac OS X) and is almost a necessity when working on large projects. The make command, when invoked will read rules from a makefile and build your code using those rules.

[edit] What is a Makefile?

A makefile is a simple text file with rules in it describing how to compile and link your program. A makefile can be extremely simple or very complex, depending on the project. For the things you do at school they will be fairly simple.

[edit] Components of a Makefile

  • Comments - anything starting with a #
  • Macros - special characters and constants
  • Rules - things to do

A rule consists of a target (what to make), dependencies (what is needed), and commands to build the target.

[edit] An Example Makefile

# Main Project
# By Daniel G. Taylor

# Macros
CXXFLAGS = -Os

# Rules
all:: main

main: main.cpp main.h
    g++ -o main $(CXXFLAGS) main.cpp

clean:
    rm -rf *.o main

The makefile above starts with a few descriptive comments and then defines a few macros that contain compiler and/or linker flags (in this case we tell the compiler to optimize code for smaller size). Next is a special rule called all that tells make what targets to look for. In this case we are looking for a target called main. Next is the rule to make main and it says that it depends on main.cpp and main.h, two source files. Whenever they change make will build main again. The next line must be indented with a tab and contains the command that make should issue to build main. After that is a rule called clean that will remove intermediate object files and the main program.

[edit] Seems Easy Enough, but How Do I Use It?

To use the makefile you can save the above into a file called makefile or Makefile. Then, in a terminal, invoke the make command:

$ make
g++ -o main -Os main.cpp
$ ./main
... runs your program here ...
$ make clean
rm -rf *.o main

The first command will build your project (assuming you actually have a main.cpp and main.h). The second will run your program and the third will clean everything that was built (in this case just the main program). You can manually invoke any target by typing its name after the make command. For example, you could do make main to build the main target. The all target is just a convenience to keep you from having to type your default target all time.

[edit] Interesting and Useful Stuff

There are some interesting and useful macros and special characters that can help you keep your makefiles short and to the point.

To create a catch-all rule for certain file types you can use the % character in the rule. When writing the command, use $@ for the target name and $< for the first dependency.

%.o: %.c %.h
    gcc -o $@ $<

In the above example we told make how to build our object file from the C source and header, however one of the neat things about make is that it knows how to build C and C++ code already, so we could just as well have written the rule with no commands,

%.o: %.c %.h

[edit] Skeleton Makefiles

Here are some makefiles you can copy and use as starting points for your projects!

[edit] Simple Single-file Project

# Example Simple Makefile
# Suitable for a single file project with no headers
# Author's Name Here

# Macros - edit these for your project
PROJECT = foo
CFLAGS = -Os

# Rules
all:: $(PROJECT)

$(PROJECT): $(PROJECT).cpp

[edit] Multiple-file Object Oriented Project

# Example OOP Makefile
# Suitable for a project with multiple files and headers
# Author's Name Here

# Macros - edit these for your project
PROJECT = foo
OBJECTS = foo1.o \
          foo2.o \
          foo3.o

CFLAGS = -Os

# Rules
all:: $(PROJECT) $(OBJECTS)

$(PROJECT): $(PROJECT).cpp $(OBJECTS)

%.o: %.cpp %.h

clean:
	rm -rf *.o

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